1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor pellet that has a plurality of chips, and also relates to a method for assembling the semiconductor devices.
2. Description of the Prior Art
Since a semiconductor device is limited in its high speed operation because of its delay in conductive lines, it is often necessary that a device's length-to-width ratio of chip is decreased to obtain its high speed operation in spite of fabrication difficulties. For a semiconductor device with a large length-to-width ratio of, for example, 10:2, it is difficult to dice, and such a device could also be damaged during fabrication processes after dicing, because it is impossible to hold itself, at its large length-to-width ratio. In assembling and wire-bonding processes, this device could also be damaged for the same reason. If the device is molded with resin, its substrate warps and its passivation film cracks due to both heat and stress. It also occurs that the device is made less moisture-proof from substrate cracking. All of these factors cause a remarkable decrease in fabrication yield of the device.
It has been known that if length-to-width ratio is set less than about 3:1, then it is possible to avoid the above mentioned problems because of the experience gotten through so many fabrications of semiconductor devices so far. However, it is difficult to handle the semiconductor devices, if their chip areas are too small. So it is necessary to keep somewhat large areas of the devices to promote the increase in their handling capabilities.
In view of handling capability, a chip with a large area takes an advantage of small area, as mentioned above. However, in view of high speed operation, the chip with a small area takes an advantage of large area, because the former can decrease delays in conductive lines. Thus there is a dilemma between chips with large and small areas. So it is advantageous to fabricate a semiconductor device that has a large handling area even with a small circuit area. One way to realize this point is a method of grouping a plurality of semiconductor devices into a pellet; mounting the pellet on a chip carrier; and wire-bonding only a part thereof. For this purpose, it is necessary to fabricate a variety of integrated circuits in a semiconductor wafer.
It is, however, difficult to fabricate simultaneously a variety of integrated circuits in a small amount. A technique to overcome this difficulty is proposed in the Japanese laid-open patent publication No. 62-72155. The proposed technique provides a method for fabricating integrated circuits (chips) as follows: making a pellet pattern that a variety of chip patterns are grouped; making a photo-mask that has repeated pellet patterns; making a wafer by using the photo-mask in photolithography process; and dicing pellets from the wafer so as to locate a chip that has a predetermined function or characteristic at predetermined corner of a chip carrier. Because this technique groups a variety of chip patterns into a pallet pattern, the process lines can fabricate a variety of chips at all times. So the proposed technique makes it possible to fabricate simultaneously a variety of integrated circuits in a small amount, besides in low cost.
FIG. 1, FIG. 2, and FIG. 3 are schematic views of the above mentioned technique. In FIG. 1, four kinds of the integrated circuits (chips), called A, B, C, and D, are grouped into a pellet 1. On the other hand, electrically conductive leads are formed at the bottom and side of a chip carrier for the pellet 1. Now the chip A has predetermined function, so the chip A is located at the bottom of the left side of the pellet 1.
If the chip D has a predetermined function, the chip D is located at the bottom of the left side of the pellet 1 as shown in FIG. 2. Assuming that the pellet 1 is identical in both FIG. 1 and FIG. 2 and if pellet shown in FIG. 1 turns around the central point thereof by 180 degrees, the pellet shown in FIG. 2 can be obtained. Any pellet of both FIG. 1 and FIG. 2 can be obtained by dicing a pellet from a wafer by locating the chip that has a predetermined function at the bottom of the left side of the pellet 1.
After pellets have been diced, wire-bonding is conducted. FIG. 3 shows wire-bonding process for the pellet shown in FIG. 1. Electrically conductive leads 5 are formed at the bottom and left side of a chip carrier for the pellet 1. Each chip has bonding-pads 7 at the position corresponding to the leads 5. The electrically conductive leads 5 and the bonding-pads 7 are interconnected with bonding-wires 11.
As shown in FIG. 3, the chip A that has a predetermined function is mounted at the bottom of the left side of the chip carrier, and electrically conductive leads 5 are formed at the bottom and the left side of the chip carrier. So it is possible to shorten bonding-wires 11 interconnecting between the chip A and leads 5. This makes it easy to fabricate devices and to promote the increase in their speed of operation.
As mentioned above, the proposed technique is a method that wire-bonding is conducted between a chip carrier and only a chip that is selected among the grouped chips which form a pellet. For example, in FIG. 3, wire-bonding is conducted only between a chip carrier and the chip A that has predetermined function, whilst and other chips B, C, and D are not wire-bonded, which form a pellet with the chip A and support it mechanically. A pellet has larger area than that of each chip, so the pellet is strong and easy to handle.
The proposed technique, however, has not only the advantages mentioned above, but also disadvantages like this: only one chip is used among the pellet which has a plurality of usable chips. For example, only the chip A is used while the others, B, C, and D are not used in FIG. 3. If the chip A is no good, the pellet is also no good although one of other chips B, C, and D is good. This causes a decrease in fabrication yield of the pellet. Since bonding-pads 7 are positioned at the fixed portion of the chip according to leads 5 of the chip carrier, only one chip can be wire-bonded. Therefore none of good chips B, C, and D can be used instead of the bad chip A in FIG. 1.